Modeling and Implementation of a Specific Microprocessor to Enhance the Performance of PLCs Employing FPGAs

Authors

Marcelo Delgado-del-Carpio Department of Electronic Engineering, National University of San Agustin of Arequipa, Arequipa, Peru PE https://orcid.org/0000-0002-6225-6306
A. Hilario-Tacuri Department of Electronic Engineering, National University of San Agustin of Arequipa, Arequipa, Peru PE https://orcid.org/0000-0001-6951-0162
Carlos A. Hernández-Gutiérrez National Technological Institute of Mexico, Tuxtla Gutierrez, México MX https://orcid.org/0000-0001-6951-0162

DOI:

https://doi.org/10.37256/jeee.2220233421

Abstract

This work presents the design of a microprocessor synthesized in FPGA based on the IEC 61131-3 standard. We report the architecture, and the operation of the internal hardware which allows the execution of Instruction List (IL). One of the most important components is the operands_selector block which allows memory elements, inputs, or outputs of the microprocessor to be treated as operands. Two ALUs are available to perform a bit, integer, and floating-point operations. The implementation of this microprocessor allows concluding that our designed microprocessor implemented in xc7a100tcsg324 (Xilinx) or EP4CE10E22C8 (Intel) FPGAs is superior in their execution times compared to the microprocessor evaluated in early studies and to one of the S7-1500 family processor.

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Published

2023-09-29

How to Cite

[1]

M. . Delgado-del-Carpio, A. . Hilario-Tacuri, and C. A. Hernández-Gutiérrez, “Modeling and Implementation of a Specific Microprocessor to Enhance the Performance of PLCs Employing FPGAs”, Journal of Electronics and Electrical Engineering, Volume 2 Issue 2 (2023), Sep. 2023.

Issue

Journal of Electronics and Electrical Engineering, Volume 2 Issue 2 (2023)

Section

Research Article

License

This work is licensed under a Creative Commons Attribution 4.0 International License.